The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, particularly to a method of manufacturing a semiconductor device and a semiconductor device which are preferable for producing a multi-layer wiring structure by use of a copper (Cu) wiring.
In recent years, attendant on the enhancement of the degree of integration of semiconductor integrated circuit devices (LSIs), the wiring process technology in relation to the higher-speed operation of the LSIs has become deemed more and more important. This is because the increase in the wiring delay time has become conspicuous due to miniaturization of semiconductor devices. For suppressing the increase in the wiring delay time, it is desirable to reduce the wiring resistance and the inter-wiring capacity.
In regard of the reduction in the wiring resistance, investigations have been made of the copper (Cu) wiring which is lower in resistance, as compared with the aluminum alloy wiring which has hitherto been used. On the other hand, in regard of the reduction in the inter-wiring capacity, investigations have been made of insulation films lower in dielectric constant (lower dielectric constant films) as compared with silicon oxide which has hitherto been used as a layer insulation film. It is considered important to introduce a multi-layer wiring structure using a Cu wiring and a low dielectric constant film.
The multi-layer wiring structure as above-mentioned is generally formed by a trench wiring method such as the dual Damascene process (see, for example, G. B. Alers, Electromigration Improvement with PDL TiN(Si) Barrier in Copper Dual Damascene Structure, “INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS”, (USA) IEEE, 2002). In such a multi-layer wiring structure, the via is used in the case of connecting upper and lower wirings; in many cases, generally, a structure is adopted in which the via bites into the lower layer wiring side (see, for example, Jason Gill, Investigation of Via-Dominated Multi-Modal Electromigration Failure Distributions in Dual Damascene Cu Interconnects with Discussion of the Statistical Implication, “INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS”, (USA) IEEE, 2003). Such a structure is called as an anchor structure, which can conduct the reduction of the wiring resistance by increasing the region of joint between the lower layer wiring and the via.
Here, one example of the method of producing a multi-layer wiring structure in which an anchor structure is formed by use of the dual Damascene process will be described referring to FIGS. 8A to 8B. As shown in FIG. 8A, a lower wiring 15 composed of Cu is provided on the upper side of a wiring trench 13 provided in a layer insulation film 12 on a substrate 11, with a barrier film 14 therebetween. An etching stopper film 16 composed of silicon carbonitride (SiCN) is formed in the condition of covering the lower layer wiring 15 and the layer insulation film 12, and thereafter a low dielectric constant film composed of methyl hydrogen silsesquioxane (MSQ) is formed as a layer insulation film 17 on the etching stopper film 16. Next, a resist mask R provided with a connection hole pattern is formed on the layer insulation film 17 by an ordinary lithographic technique.
Subsequently, as shown in FIG. 8B, etching is conducted using the resist mask R, whereby the layer insulation film 17 is provided with a connection hole 18 reaching the etching stopper film 16. Thereafter, the resist mask R is removed.
Next, as shown in FIG. 8C, a resist mask (omitted in the figure) provided with a wiring trench pattern is formed on the layer insulation film 17 by an ordinary lithographic technique, and thereafter the layer insulation film 17 is provided with a wiring trench 19 in the state of being communicated with the connection hole 18, by etching using the resist mask. Thereafter, the etching stopper film 16 exposed at a bottom portion of the connection hole 18 is removed, whereby the surface of the lower wiring 15 is exposed.
Subsequently, as shown in FIG. 8D, by sputter etching using Ar, the surface side of the lower wiring 15 exposed at the bottom portion of the connection hole 18 is dug, thereby causing the connection hole 18 to reach the inside of the lower wiring 15.
Next, as shown in FIG. 8E, a barrier film 20 is formed on the layer insulation film 17 in the condition of covering the inside walls of the connection hole 18 and the wiring trench 19.
Next, as shown in FIG. 8F, a wiring material film 21 composed of Cu is formed on the barrier film 20 in the condition of filling up the connection hole 28 and the wiring trench 19 provided with the barrier film 20. Subsequently, a heat treatment is carried out, to cause crystal growth of Cu in the wiring material film 21.
Subsequently, as shown in FIG. 9, the wiring material film 21 (see FIG. 1F) and the barrier film 20 are removed by a chemical mechanical polishing (CMP) process until the surface of the layer insulation film 17 is exposed, thereby forming an upper layer wiring 22 in the wiring trench 19 and forming a via 23 in the connection hole 18. As a result, the via 23 is provided in the state of reaching the inside of the lower layer wiring 15, whereby an anchor structure in the condition where the via 23 bites into the lower wiring layer 15 is formed.
In addition, other than the manufacturing method described using FIGS. 8 to 9, a manufacturing method as follows is also carried out generally. First, as has been described using FIG. 8C, the procedure up to the step of removing the etching stopper film 16 at the bottom portion of the connection hole 18 to thereby expose the surface side of the lower wiring 15 is carried out in the same manner as in the above-described manufacturing method. Next, as shown in FIG. 10A, a first barrier layer 20a is formed on the layer insulation film 17 in the state of covering the inside walls of the wiring trench 19 and the connection hole 18.
Subsequently, as shown in FIG. 10B, by sputter etching using Ar, the first barrier layer 20a at the bottom portion of the connection hole 18 is removed, and the surface side of the lower layer wiring 15 is dug, thereby causing the connection hole 18 to reach the inside of the lower layer wiring 15.
Thereafter, as shown in FIG. 10C, a second barrier layer 20b is formed on the first barrier layer 20a in the state of covering the inside walls of the wiring trench 19 and the connection hole 18, thereby forming a barrier film 20 composed of the first barrier layer 20a and the second barrier layer 20b. The subsequent steps are carried out in the same manner as in the manufacturing method described above referring to FIGS. 8F to 9.